MathWorks Speeds Up FPGA-in-the-Loop Verification

MathWorks announced new capabilities in HDL Verifier to speed up FPGA-in-the-loop (FIL) verification. The new FIL capabilities enable faster communication with the FPGA board and higher clock frequency simulation.

NEW DELHI: Now, system engineers and researchers can confidently and quickly verify and validate that an FPGA design works as expected in the system, saving development time.

With increasing complexity of signal processing, vision processing, and control system algorithms, simulating hardware implementation on an FPGA board helps validate the design in its system context. HDL Verifier for FIL verification automates the setup and connection of MATLAB and Simulink test environments to designs running on FPGA development boards. This helps to deliver high-fidelity cosimulations of the FPGA designs running on actual hardware, while reusing the same test environment used for development.

The R2016b release allows engineers to specify a custom frequency for their FPGA system clock, with clock rates up to five times faster than previously possible with FIL. And for designs that use overclocking factors when targeting an FPGA, such as control applications, larger data output sizes can be used to increase throughput. Engineers can now also utilize FIL (using the PCI Express interface) to speed up communications between MATLAB and Simulink, and Xilinx KC705/VC707 and Intel Cyclone V GT/Stratix V DSP development boards, with simulation speeds 3-4 times faster than Gigabit Ethernet.

“As electronic systems become more complex, the need to accurately prototype as a validation step becomes vital,” said Jack Erickson, product manager at MathWorks. “HDL Verifier now allows engineers to run designs on real hardware, at realistic clock frequencies, and with fast runtimes. Being able to do this from MATLAB and Simulink is an easy way to validate hardware design within the algorithm development environment.”